Via Current, Diameter & Temp Rise Calculator for PCB Design

Choosing the right via size is a trade-off between current capacity, manufacturability, and space.

• Standard Vias: 0.2mm - 0.5mm (8-20 mils) are common for signals.
• Power Vias: Larger vias (0.5mm+) or arrays of smaller vias are preferred for power rails to minimize resistance and inductance.
• Plating: Standard plating is often 25μm (approx 1 mil). Thicker plating increases current capacity without increasing hole diameter.

Multiple Vias

If a single via cannot handle the required current, use the Number of Vias field. Using multiple vias in parallel distributes the current/heat and reduces total inductance.

Tip: When using multiple vias for high current, don't assume perfect sharing. It's often safer to derate the capacity of the array (e.g., assume 80-90% efficiency) due to uneven geometry or thermal saturation.

Definition

A Via (Vertical Interconnect Access) is a plated hole that allows electrical connection between different layers of a PCB. The performance and allowable DC current are controlled by the conductor cross-sectional area (the copper barrel), thermal environment, and plating geometry.

IPC-2221 Formula (overview)

This calculator uses the IPC-2221 empirical relation for external conductors to estimate the maximum steady-state current ($I$):

$$ I = k \cdot (\Delta T)^{0.44} \cdot A^{0.725} $$

Where:

• k: Empirical constant (0.048 for external layers, 0.024 for internal layers in IPC-2221). We use the external value by default.
• ΔT: Permissible temperature rise above ambient (°C).
• A: Conductor cross-sectional area (in the units expected by the formula — IPC historically uses mils², this calculator converts units automatically).

Conductor Cross-Section — plated vs filled vias

The physically relevant area is the copper conductor area, not the empty hole. There are two common cases:

1. Plated (annular) via — hollow copper barrel:

   The exact annulus cross-sectional area (using consistent linear units) is:

   $$ A = \pi\,\bigl(d\,t + t^{2}\bigr) $$

   Derivation (annulus)

   Start from the difference of outer and inner circle areas. Let the outer radius be $R_{\mathrm{out}}=d/2 + t$ and the inner radius $R_{\mathrm{in}}=d/2$. Then:

   $$ A = \pi\left(R_{\mathrm{out}}^{2} - R_{\mathrm{in}}^{2}\right) $$

   Substitute the radii:

   $$ A = \pi\left(\left(\frac{d}{2} + t\right)^{2} - \left(\frac{d}{2}\right)^{2}\right) $$

   Expand the square:

   $$ A = \pi\left(\frac{d^{2}}{4} + d\,t + t^{2} - \frac{d^{2}}{4}\right) $$

   Cancel the $d^{2}/4$ terms and simplify:

   $$ A = \pi\left(d\,t + t^{2}\right) $$

   For typical plated vias where $t \ll d$, the quadratic term is negligible and the common approximation is:

   $$ A \approx \pi\,d\,t \qquad (\text{when } t \ll d) $$
2. Filled via (solid copper):

   Use the full circular cross-section:

   $$ A = \pi \left(\frac{d}{2}\right)^{2} $$

Note: IPC-2221 tables and examples historically use mils². This calculator accepts user inputs in mm, μm, mil, etc., and converts to the correct units internally before applying the IPC formula.

Inductance & Impedance (HF guidance)

A simple via inductance estimate (useful for low-GHz reasoning) is:

$$ L_{\mathrm{nH}} \approx 0.2\,h_{\mathrm{mm}}\,\Bigl[1+\ln\bigl(4h_{\mathrm{mm}}/d_{\mathrm{mm}}\bigr)\Bigr] $$

Formula referenced from High-Speed Digital Design: A Handbook of Black Magic (Howard Johnson & Martin Graham).

Where h (via length) and d (via diameter) are in millimetres and the result is in nanohenries (nH). To convert inductance to complex impedance at frequency f (Hz):

$$ Z_{L} = j\,2\pi f L \quad\text{and}\quad |Z_{L}| = 2\pi f L \; (\Omega) $$

Keep in mind that at higher frequencies skin and proximity effects change both the effective resistance and current distribution; the simple DC annulus area → IPC current estimate is only a thermal/DC approximation. For accurate signal-integrity or RF behavior use an EM solver or S-parameter measurement.

Multiple Vias

As a first-order model, inductance and conductor area scale with the number of identical vias in parallel:

$$ L_{\mathrm{total}} \approx \frac{L_{\mathrm{single}}}{N}, \qquad A_{\mathrm{total}} = N\,A_{\mathrm{single}} $$

These equalities assume widely spaced, uncoupled vias and even current sharing. In practice mutual coupling, thermal interaction and unequal current division mean you should derate the simple linear result (or run a thermal/EM simulation) for tightly packed via arrays.

While useful, this standard model has limitations:

1. DC Only: The current calculations assume DC or low-frequency AC. At high frequencies, Skin Effect reduces the effective cross-sectional area, increasing resistance.
2. Conservative Standard: IPC-2221 is an older standard. Newer physics-based models (IPC-2152) can yield different results but require more complex environmental inputs.
3. Isolated Vias: The thermal calculation assumes the via is thermally isolated. Vias connected to large copper planes will have better heat sinking (handling more current), while closely packed via farms might heat up each other (handling less).